Our research, in practice

Technologies

Demonstrating our Research

Our technologies demonstrate our research findings, through the fabrication of experimental test chips and the release of downloadable software tools.

Chip Demonstrators

Our test chips allow researchers to practically validate new designs and approaches, and are a central part of the Centre’s activities.

COILS-C1

COILS-C1, taped-out out in November 2018, is the latest in a series of test-chips investigating low-cost 3D die stacking using near-field wireless communication. This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in…

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ICLexperimenter-2018

Taped-out in May 2018, ICL-Experimenter is the first in a series of Arm-ECS research centre test-chips designed to explore wireless 3D integration using inductive coupling links. The chip was fabricated in AMS 0.35um technology with two vertically stacked dies within…

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Pipistrelle-4

Pipistrelle-4, taped-out at the end of May 2017, is the latest in a series of low-energy sensor-system chips. The chip includes circuit/system ideas from multiple PhD research students and industry, focusing on an energy and performance optimised SRAM bitcell, low-area…

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ECStest-2016

Taped-out in October 2016 this test-chip was designed to explore on chip wireless communication in the mm-wave frequency band. The chip was fabricated in an AMS 0.35um technology and incorporates two meander monopole antennas (which can be observed in the…

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Pipistrelle-3

Taped out in March 2016, this chip advanced Pipistrelle-2’s design by adding forward body-bias to improve performance at low voltage as well as an autonomous dynamic voltage and frequency scaling (DVFS) control state machine for carefully sequencing clocks, regulator settings…

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Pipistrelle-2

This chip advances Pipistrelle-1’s design, taking another step towards filling in the pieces required to build an autonomous minimum-energy sensor system. Low power clock sources are an important part of a minimum energy system for driving CPUs, switched-capacitor converters, power-management…

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Pipistrelle-1

A sub-threshold demonstrator chip, incorporating innovative features for energy harvesting and power conversion, has been designed and taped-out by Arm R&D engineers and ECS researchers. Pipistrelle-1 Minimum energy systems are important for deployable multi-billion wireless sensor networks (WSNs). This sub-threshold…

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Cricket-1

This demonstrator, code-name “Cricket-1”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Cricket-1 was taped out in September 2013, arriving back from fab in January…

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Tokachi-4M

This low-power technology demonstrator, code-name “Tokachi-4M”, contains 16x Cortex-M0 CPU cores and was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-4M was taped out in…

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Tokachi-4A

This advanced state-retention power-gating demonstrator, code-name “Tokachi-4A”, contains a Cortex-M0 system control processor and a dual-core Cortex-A5 application processor subsystem, again designed as a collaboration with Arm Ltd on TSMC 65nm Low-Power process technology available. Tokachi-4A was taped out in…

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Tokachi-3M

This demonstrator, code-name “Tokachi-3M”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3M was taped out in March 2012. Tokachi-3M IP watermarking demonstrator, TSMC65LP

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Tokachi-3A

This demonstrator, code-name “Tokachi-3A”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3A was taped out in March 2012, packaged and delivered in July 2012…

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Tokachi-1 and 2

Tokachi-1 and -2 technology demonstrators were taped out and manufactured in 2011 to showcase research into register state integrity and advanced power gating and state retention techniques that build on the capabilities that are now well supported by current EDA…

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Software Tools

Our software tools are released to the community so that others can benefit from our research findings and methodologies.

Fused: Full-System Simulation of Energy-Driven Computers

Fused is a full-system simulator for modelling energy-driven computers. To accurately model the interplay between energy-availability, power consumption, and execution; Fused models energy and execution in a closed feedback loop. The power model is based on recording high-level events (memory…

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COIL-3D

COIL-3D is a CAD tool for determining best performing inductor geometries for use in Inductive Coupling Link (ICL) based Three Dimensional Integrated Circuits (3D-ICs), developed at the University of Southampton, in collaboration with Arm Research. The tool takes as its…

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GemStone: Hardware-Validated CPU Performance and Energy Modelling

GemStone is a suite of five software tools that, together, identify and evaluate the sources of error in gem5 models against a reference hardware (HW) platform by utilising statistical and machine learning approaches. Independently, the tools serve many purposes: Automating…

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PowMon: Accurate and Stable CPU Power Estimation

Being able to accurately estimate CPU power consumption is a key requirement for both controlling online CPU energy-saving techniques and design-space exploration. Models built and validated using measured data from an actual device are extremely valuable as their accuracy is…

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NIRGAM: A Simulator for NoC Interconnect Routing and Application Modeling

NIRGAM is a systemC based discrete event, cycle accurate simulator for research in Network on Chip(NoC). It provides substantial support to experiment with NoC design in terms of routing algorithms and applications on various topologies.

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