Tokachi-3A Technology Demonstrator

This demonstrator, code-name “Tokachi-3A”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc.

Tokachi-3A was taped out in March 2012, packaged and delivered in July 2012 and has supported evaluation of place-and-route strategies for IP watermarking.


The Tokachi-3A technology demonstrator – TSMC65LP

The chip includes a soft Watermark Circuit integrated into Cortex – A5 (TM) CPU to showcase the University of Southampton project on IP Watermarking of Embedded Processor Cores.

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