This demonstrator, code-name “Cricket-1”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Cricket-1 was taped out in September 2013, arriving back from fab in January 2014. It supports evaluation of area and power reduction techniques for IP watermarking. Cricket-1 IP watermarking demonstrator, TSMC65LP

This low-power technology demonstrator, code-name “Tokachi-4M”, contains 16x Cortex-M0 CPU cores and was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-4M was taped out in October 2012 and up and running on the bench late January 2013, and includes sub-threshold voltage experimental circuits and an IP watermarking characterization block. Tokachi-4M   Tokachi-4M

This advanced state-retention power-gating demonstrator, code-name “Tokachi-4A”, contains a Cortex-M0 system control processor and a dual-core Cortex-A5 application processor subsystem, again designed as a collaboration with Arm Ltd on TSMC 65nm Low-Power process technology available. Tokachi-4A was taped out in October 2012 and working and in characterization at the end of January 2013, and the silicon includes an alternative implementation of the IP watermarking research circuitry. Tokachi-4A

This demonstrator, code-name “Tokachi-3M”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3M was taped out in March 2012. Tokachi-3M IP watermarking demonstrator, TSMC65LP

This demonstrator, code-name “Tokachi-3A”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3A was taped out in March 2012, packaged and delivered in July 2012 and has supported evaluation of place-and-route strategies for IP watermarking. The Tokachi-3A technology demonstrator – TSMC65LP