Techniques and Validation for Protection of Embedded Procesoors
Technology scaling allows complex systems to be placed on a single die. To tackle this complexity it is increasingly desirable to source sub-systems, such as CPUs, from external Intellectual Property (IP) suppliers.
The risk of unauthorized use has become critically important to IP vendors. Although methods for securing an IP exist, they often do not provide physical protection and EDA tools are far from universal and pain-free. As a result, auditing the presence of IP in finished products is an important challenge for IP providers. De-encapsulation and die-level reverse engineering can be used to prove the presence of IP but the process is slow and costly. It is therefore desirable to identify and prioritize IP candidates to be short-listed for more thorough investigation. One commonly used detection method is digital watermarking which provides proof of the ownership to the IP vendor.
This research aims to improve watermarking technique by investigating sequences used to generate a watermark as well as implementing a watermark in a soft IP processor core as a part of the design flow. Finally, new and more effective detection techniques are investigated.
Tokachi 3 Test Chip
