Tokachi-3M Technology Demonstrator

This demonstrator, code-name “Tokachi-3M”, was designed as a collaboration with Arm Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3M was taped out in March 2012.


Tokachi-3M IP watermarking demonstrator, TSMC65LP

The chip includes a hardened Watermark Circuit and Noise Generator macro block as well as Cortex – M0 (TM) CPU to showcase the University of Southampton project on IP Watermarking of Embedded Processor Cores.

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