Tokachi-1 and 2
Tokachi-1 and 2 Technology Demonstrators
Tokachi-1 and -2 technology demonstrators were taped out and manufactured in 2011 to showcase research into register state integrity and advanced power gating and state retention techniques that build on the capabilities that are now well supported by current EDA tools and implementation flows.
Building on the multi-voltage tools enhancements the initial technology demonstrator, code-name āTokachi-1ā, was designed as a collaboration with Arm Ltd who provided microprocessor core technology and latest State-Retention Power-Gating (SRPG) power management kits to augment the Physical IP for the 65nm Low-Power process technology available from TSMC Inc.
Tokachi-1 low power technology demonstrator, TSMC65LP
The chip includes 14 Cortex-M0 (TM) CPUs configured to showcase a range of low-power implementation techniques using the industry standard āUnified Power Formatā (UPF) power intent to infer voltage domains, isolation clamp strategies, power-gating inference and state retention intent to the RTL design. Tokachi-1 was taped out in April 2011.
The University of Southampton experimental technology demonstrator contents are primarily:
- State Retention integrity and robustness analysis
- Sub-Clock State-Retention Power Gating for ultra low power energy harvesting applications
The complex design implementation has 5,126,848 transistors and includes 14 x Cortex-M0 processors (9 unique macrocells). The multi-voltage design has 13 separate power domains, with a common VSS ground, 3 independent VDD core supplies, 1 gate bias supply rail and three analogue pads to observe power gated āvirtualā supply rails. 32Kbyte of SRAM are included on-chip to provide zero- wait-state code and data memory and an additional 2Kbyte of flip-flop memory are synthesized for the state integrity structures. The silicon is packaged in an 84-pin JLCC device, is fully operational, and was evaluated and characterized and executed software benchmarks for analysis.
Tokachi 2 was an enhanced design based on Tokachi 1 to improve the clock modulation range for the sub-clock Cortex-M0 processor and expand the power-gating control measurement capabilities (taped out October 2011).
Technology:
TSMC65LP
Die-size:
1.875 x 1.875 mm
Features:
14 Cortex-M0 processors
(9 unique macrocells)
13 separate power domains
Related Projects
Related People
Related Theses
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Mistry, Jatin N. (2013) Leakage power minimisation techniques for embedded processors. University of Southampton, Faculty of Physical & Applied Science, Doctoral Thesis, 210pp.Feb 2013