Leakage Power Minimisation for Embedded Processors

In a large number of pervasive computing examples such as wireless sensor nodes, RFID or personal health care/monitoring, an electronic device is deployed in the field and can be expected to operate without maintenance forever.

The constraint imposed by battery life has resulted in energy harvesting being increasingly used as a method to power a device by scavenging ambient energy from the environment. However, low energy availability results in an energy harvesters output power being severely constrained demanding both high energy efficiency and very low power from the electronics.

Tokachi 1 showing the macrocell containing sub-cycle leakage technologies

The research in this project identifies that the fundamental building block of all of these systems is the microprocessor and aims to reduce its power consumption to help meet the power budget of an energy harvester. The work typically done by a microprocessor in these devices allows performance to be lowered to reduce power but comes at the cost of energy being wasted to leakage (power dissipation due to non-ideal properties) rather than being consumed for useful work. As part of the research we develop new leakage power minimisation techniques that can be used in digital circuits during the active mode to reduce the energy that is wasted to these parasitic effects. Primarily, the Sub-Clock Power Gating technique developed in this project capitalises on the idle time of combinational logic, that results from aggressive clock frequency scaling, to power gate it within the clock period to improve overall energy efficiency.

Awards: SNUG Silicon Valley 2012, Technical Committee Award – Best Technical Paper