Tokachi-1 and -2 technology demonstrators were taped out and manufactured in 2011 to showcase research into register state integrity and advanced power gating and state retention techniques that build on the capabilities that are now well supported by current EDA tools and implementation flows. Building on the multi-voltage tools enhancements the initial technology demonstrator, code-name “Tokachi-1”, was designed as a collaboration with Arm Ltd who provided microprocessor core technology and latest State-Retention Power-Gating (SRPG) power management kits to augment the Physical IP for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-1 low power technology demonstrator, TSMC65LP The chip…