The ARM-ECS Research Centre was founded in 2008, and is a collaboration between researchers in the Department of Electronics and Computer Science at the University of Southampton, and ARM Research, Cambridge. On the back of winning the NMI University Research Group of the Year award at the end of 2015, the ARM-ECS Research Centre had a series of successes in 2016.
ARM-ECS Research Center
The industry-University Centre was founded in 2008 following successful research collaboration over a number of years prior between Prof Al-Hashimi's research group and ARM (Cambridge). The centre is based at Electronics and Computer Science (ECS), University of Southampton, but its researchers work at ARM or at ECS with internships at ARM. It is Co-directed by Prof-Al-Hashimi, and Dr David Flynn (ARM Fellow, Visiting Professor at ECS). The centre focuses on leading-edge research on advanced design methods, architectures and their practical validations for energy-efficient and dependable single-core and multi-core processor systems.
Currently PhD research projects are being carried out in the Centre, funded by ARM, EPSRC and the University of Southampton. Each project has a one or more industrial mentors from ARM in addition to the academic supervisors from ECS. Some PhD students are based at ARM, and others are based at ECS, and typically each student spends three months interning at ARM each year.
More information on this here.
Off and On Again .....
Charlie Leech, one of the ARM-ECS Centre’s PhD students, has successfully completed a three month internship at ARM Research, Cambridge. Charlie’s internship was funded by a competitively awarded HiPEAC Collaboration grant, which allowed him to be based at ARM from September to December 2016.
Last month, a team of 13 academics and researchers from the ECS, University of Southampton joined 9 researchers from ARM R&D in Cambridge for the first biannual review meeting of 2017. The purpose of these meetings is to discuss research progress in existing areas of collaboration (e.g. energy-efficient system-level-design, and the internet of things), as well as identifying new strategic research areas for future activities. The full-day's meeting saw 9 presentations from ECS researchers, and 4 from ARM researchers.
An ARM-ECS paper describing a cutting-edge design for supply-independent oscillators has been accepted for presentation at the International Solid State Circuits Conference 2017.
Yunpeng Cai, a PhD student from the University of Southampton, will be undertaking a four-month internship at ARM Cambridge starting in December 2016. His research is focussed on the design of building blocks for ultra low-power systems.
Many congratulations and best wishes....
Having successfully defended....
Sascha carried out the majority of his PhD research at ARM Cambridge working closely with Andreas Hansson. We wish him well as he now returns to ARM as a full-time employee of the Architecture and Technology team working on projects related to his PhD thesis.
The ARM-ECS Research Centre won the title ‘University Research Group of the Year’ at the National Microelectronics Institute annual dinner and prizegiving event, held last night (19 November) in London. The award was sponsored by Thales for excellent liaison and partnership in electronic systems with industry. The citation read: ‘This year’s winner has demonstrated a very strong portfolio in electronics design built on world-class research partnerships with companies.
Congratulations to Jedrzej Kufel on his recent viva success. Jedrzej's PhD research has been undertaken in the Centre, whilst benefiting from ARM's expertise and IP. We now wish him well as he returns to ARM in Cambridge as a full-time time employee in the Embedded Web team in Internet of Things Business Unit.
Jedrzej's PhD research has been undertaken in the Centre, during which he has also spent time at ARM as a research intern. We now wish him well as he joins ARM in Cambridge as a full-time employee in the Research and Development, Internet of Things team.
Congratulations to Matthias Boettcher on his recent viva success. Benefiting from ARM's expertise and IP while conducting his research at their Cambridge offices, Matthias filed for several US and UK patents in addition to publicising his work at international venues. We wish him well as he now returns to ARM as a full-time employee of the Research and Development team.
Working with partners in ARM, Altera and BT, Dr Rob Maunder, Prof Bashir Al-Hashimi and Prof Lajos Hanzo will use this three-year grant to develop wireless receiver algorithms and architectures that offer processing throughputs that are an order of magnitude higher than the State-Of-the-Art (SOA).
Congratulations to Sheng Yang on successfully defending his PhD thesis in a recent viva and now becoming Dr Yang! Sheng PhD research has been undertaken in the Centre, during which he has also spent time at ARM as a research intern.
Our previous research in the Glacsweb project has led to a considerable expertise in deploying wireless sensor networks there to monitor glacier and climate changes (see www.glacsweb.org). We are now building a trial of "internet of things" connected sensor nodes to monitor some real world data by using a combination of our latest technologies. This is made easier by taking advantage of the systems and mechanisms we left there last summer such as weather station, cameras, wind/solar generators and seismic sensors.
Professor Al-Hashimi has been awarded a prestigious 5-year EPSRC Programme grant (£5.7M) addressing some of the key major challenges in the design and implementation of energy-efficient and reliable embedded systems with many-core processors. The grant’s academic collaborators are Imperial College London, University of Manchester and Newcastle University. The grant’s industrial collaborators are ARM, Imagination Technologies, Altera, Freescale and Microsoft Research.
Congratulations to Jatin Mistry on successfully defending his PhD thesis in a recent viva and now becoming Dr Mistry! Jatin's award-winning PhD research has been undertaken in the Centre, during which he has also spent time at ARM as a research intern. We now wish him well as he joins ARM in Cambridge as a full-time employee in the Processor Division Cores Implementation team.
Warren East, CEO of ARM, gave a Distinguished Lecture titled "Enabling a Smarter Future" at the University of Southampton on Monday 3 December. Beginning with a very brief introduction to ARM technology and the ARM business model, Warren East will reviews the evolution of mobile technology over the last 10 years and assess likely demands over the next decade.
Jedrzej Kufel starts his 3 months internship at ARM Cambridge, from October 1st 2012. He is working with the R&D group on “IP Watermarking of Embedded Processor Cores”.
EPSRC has agreed to fund research for 3 years on Resilient and Testable Energy-Efficient Digital Hardware. The research will be undertaken in collaboration with ARM, Cambridge.
There is an increasing complexity in applications. Even with the power management methods like DVFS in place, if an application causes the processor to perform poorly, that will have a negative effect on power utilization.
The technology scaling allows complex systems to be placed on a single die. To tackle this complexity it is increasingly desirable to source sub-systems, such as CPUs, from external Intellectual Property (IP) suppliers. The risk of unauthorized use has become critically important to IP vendors. Although methods for securing an IP exist, they often do not provide physical protection and EDA tools are far from universal and pain-free. As a result, auditing the presence of IP in finished products is an important challenge for IP providers.
As computers are moving from the traditional large scale designs to smaller, more tightly integrated Systems-on-Chip (SoC), the complexity and the variety of applications are increasing. The IP blocks are connected using a Network-on-Chip (NoC), which employs measures to provide Quality-of-Service (QoS) guarantees for the traffic flowing though the network. Each application places specific demands on both the IPs in the SoC and the interconnect; these demands change as the running applications change.
Leakage power is a major contributor to the IC power consumption in modern electronics design. In many applications processor spend significant amount of time in idle mode. Due to the exponential relationship between leakage power and supply voltage, Idle circuit power reduction can be achieved through voltage scaling. However the reduction in supply voltage can impact the system reliability. The objectives of this work are:
- Power management policies exist, but these typically reduce performance or result in small power savings
- As some components in the system may be unused or clocked at higher frequencies than needed, some power savings can be achieved
- Energy saving opportunities can be found using adaptive Power Management HW for low-level control, without penalising overall performance
- The strategy for the design is to have low-level, localised Power Management per core
- Machine Learning is at HW (low-level control, fast response)
In a large number of pervasive computing examples such as wireless sensor nodes, RFID or personal health care/monitoring, an electronic device is deployed in the field and can be expected to operate without maintenance forever. The constraint imposed by battery life has resulted in energy harvesting being increasingly used as a method to power a device by scavenging ambient energy from the environment. However, low energy availability results in an energy harvesters output power being severely constrained demanding both high energy efficiency and very low power from the electronics.
This project aims to improve the energy efficiency of the next generation of high performance ARM processors (A15+). The current focus is improving battery lifetimes under heavy workloads such as gaming and video streaming. In current systems the cost of moving data to the processor is approximately 100,000 cycles from mass storage (hard disks), 250 cycles from main memory, 10-15 cycles from level 2 cache and 1-2 cycles from level one cache. This project aims to improve the efficiency and speed of the processor - L1 interface.
Techniques used are: