Paper Accepted in IEEE Journal of Solid State Circuits

A paper describing a novel ultra-low power single-phase clocked flip-flop has been accepted by the prestigious IEEE Journal of Solid State Circuits.

The paper describes a new 18-transistor single-phase clocked flip-flop (18TSPC). The novel topology is fully-static and contention-free, and has the lowest number of transistors reported for its type. The device was initially created by PhD student Yunpeng Cai during his studies at ECS supervised by Dr. Tom J Kazmierski and Dr. Alex Weddell. It was developed for silicon testing while on his internship at Arm Research, Cambridge, with support from Anand Savanth, Pranay Prabhat and James Myers.

The paper, entitled ‘Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS’, shows that the new design achieves a 20% cell area reduction compared to the conventional Transmission Gate Flip-Flop. The design was validated as part of the Pipistrelle 4 test-chip and experimental measurements show that the it achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

The joint research led to a granted patent and is currently being considered for use in a range of Arm processors.