Clock Distribution Networks for Many-Core Systems
As CMOS technology nodes continue to shrink, transistor gate delays get increasingly better, leading to a potential for higher system performance. However, conventional metallic interconnect exhibits smaller size and higher density, leading to an increasing global signal propagation delay. As a result of the increasing wiring resistance, capacitance and inductance, this causes a conflict between advanced technology and system frequency.
The clock signal is one of the most common global signals in any many-core/synchronous system. To reduce interconnect delay and clock uncertainties, it typically adopts a combination of clock tree and clock grid for global and local distribution respectively, using conventional interconnect at the expense of higher power consumption and area occupation.
Wireless interconnect provides a potential of jumping over conventional interconnects, therefore becoming independent of the wiring characteristics of global interconnects and reducing the overall signal propagation delay. This research aims to address the problems caused by the reducing interconnect dimension. By adopting effective analog and radio frequency techniques in terms of modulation, on-chip antenna and wireless transceivers, this research will focus on advanced low power and low latency clock distribution architecture design for synchronous systems.