A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm² 7.1mW/mm² Simultaneous Wireless Inter-Tier Data and Power Transfer
B. J. Fletcher, T. Mak and S. Das, “A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm² 7.1mW/mm² Simultaneous Wireless Inter-Tier Data and Power Transfer,” IEEE Symposium on VLSI Circuits, Honolulu, Hawaii, 2020 pp. 1-2.