Quality of Service and Quality of Experience Aware System Level Design

Quality of Service and Quality of Experience Aware System Level Design

As computers are moving from the traditional large scale designs to smaller, more tightly integrated Systems-on-Chip (SoC), the complexity and the variety of applications are increasing.

The IP blocks are connected using a Network-on-Chip (NoC), which employs measures to provide Quality-of-Service (QoS) guarantees for the traffic flowing though the network. Each application places specific demands on both the IPs in the SoC and the interconnect; these demands change as the running applications change. Therefore, the performance seen by the end user in not simply governed by the performance of the individual IPs; it is also strongly influenced by the performance of the network interconnect. Through the addition of run-time performance monitoring and adjustment of network parameters a high Quality of Experience can be maintained, whilst operating within the lowest sustainable power envelope.

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  • Bischoff, Sascha, Hansson, Andreas and Al-Hashimi, Bashir M. (2013) Applying quality of experience to system optimisation. In, 23th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2013),…
    Aug 2013

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