Run-time Adaptation of Embedded Systems for Power-Noise Issues
In the past, the very high associated design and validation cost for assuring the power integrity of SoCs could only be justified for enterprise applications. Nowadays, Internet-of-Things (IoT) applications require dependable embedded systems based on heterogeneous SoCs. However, the dependability of an application is affected by the power integrity of the SoC. At the same time, the multiple electrical states of a heterogeneous SoC have increased the cost for validating their power integrity.
In the domain of high performance mobile computing, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques make these systems limited by their power delivery and susceptible to pathological AC transients that undermine their reliability. Many studies have shown that power noise can lead to system failures, when operating frequency causes power-network to resonate. Also, the operating frequencies of these circuits are limited by their power-delivery due to the strict power budget of mobile devices that pushes operating voltage boundaries near threshold.
Near-threshold computing, though, makes these circuits more susceptible to data corruptions and system failures due to voltage noise. Voltage noise is sensitive to micro-architectural events driven by hardware and software interactions and can only be accurately evaluated online through direct measurement.
When the supply voltage droops to low values, then both dynamic and static power consumption reduce; however silent data corruptions and system crashes have been observed, which are very sensitive to inter-core process variation and the executed workload. As system designs become more complex in order to cope with a variety of applications, and the power noise depends on process variation and run-time conditions (workload, operating voltage and frequency), there is the need for run-time adaptation of the system to the exhibited power noise in order to optimize its power consumption.