Error Resilient Techniques for Storage Elements of Low Power Design
Leakage power is a major contributor to the IC power consumption in modern electronics design.
In many applications processor spend significant amount of time in idle mode. Due to the exponential relationship between leakage power and supply voltage, Idle circuit power reduction can be achieved through voltage scaling. However the reduction in supply voltage can impact the system reliability.
The objectives of this work are:
- Study the leakage power saving through voltage scaling;
- Find out the lowest data retention voltage (the supply voltage under which the storage node start to lost states);
- Find out the failure pattern, eg. which nodes failed at a certain supply voltage;
- Study if neighbouring switching activities have any impact on the reliability of storage cells;
- Provide real-time monitoring and protection for the storage cells through parity checking.
Magnified section of the Tokachi 2 test chip showing the testing area