This low-power technology demonstrator, code-name “Tokachi-4M”, contains 16x Cortex-M0 CPU cores and was designed as a collaboration with ARM Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-4M was taped out in October 2012 and up and running on the bench late January 2013, and includes sub-threshold voltage experimental circuits and an IP watermarking characterization block.

Monday, October 1, 2012