Leakage Power Minimisation for Embedded Processors

In a large number of pervasive computing examples such as wireless sensor nodes, RFID or personal health care/monitoring, an electronic device is deployed in the field and can be expected to operate without maintenance forever. The constraint imposed by battery life has resulted in energy harvesting being increasingly used as a method to power a device by scavenging ambient energy from the environment. However, low energy availability results in an energy harvesters output power being severely constrained demanding both high energy efficiency and very low power from the electronics.

Low-Power, High Performance Memory Architectures for Vector Processing

This project aims to improve the energy efficiency of the next generation of high performance ARM processors (A15+). The current focus is improving battery lifetimes under heavy workloads such as gaming and video streaming.  In current systems the cost of moving data to the processor is approximately 100,000 cycles from mass storage (hard disks), 250 cycles from main memory, 10-15 cycles from level 2 cache and 1-2 cycles from level one cache. This project aims to improve the efficiency and speed of the processor - L1 interface.

Techniques used are:

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