Dependable Embedded Processors

Magnified section of the Tokachi 2 test chip showing the testing area

Leakage power is a major contributor to the IC power consumption in modern electronics design. In many applications processor spend significant amount of time in idle mode. Due to the exponential relationship between leakage power and supply voltage, Idle circuit power reduction can be achieved through voltage scaling. However the reduction in supply voltage can impact the system reliability. The objectives of this work are:

  • Study the leakage power saving through voltage scaling;
  • Find out the lowest data retention voltage (the supply voltage under which the storage node start to lost states);
  • Find out the failure pattern, eg. which nodes failed at a certain supply voltage;
  • Study if neighbouring switching activities have any impact on the reliability of storage cells;
  • Provide real-time monitoring and protection for the storage cells through parity checking.

Tokachi-1 & 2 Test Chip (link)

The test chip used TSMC 65nm low power technology library. The design sign-off frequency is 100MHz. Two blocks of 1KB flip-flops arrays are implemented. Each block can be used to generate switching noise or for low voltage state retention. Each block has its own power rail for power control. Parity checking logic is embedded in the flip-flops arrays, and the parity storage is in a separated power domain located on the top of the chip area.

 

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