Chips

ARM-ECS chips that have been taped out or are in production.

Acknowledgement is made to the Europractice (http://www.europractice-ic.com) "MiniASIC" program through which the technology demonstrators were fabricated and packaged. (http://www.europractice-ic.com/prototyping_minisic.php)

Taped out in March 2016, this chip advanced Pipistrelle-2’s design by adding forward body-bias to improve performance at low voltage as well as an autonomous dynamic voltage and frequency scaling (DVFS) control state machine for carefully sequencing clocks, regulator settings and body-bias.

This chip advances Pipistrelle-1’s design, taking another step towards filling in the pieces required to build an autonomous minimum-energy sensor system. Low power clock sources are an important part of a minimum energy system for driving CPUs, switched-capacitor converters, power-management unit logic, wake-up timers and more.

A sub-threshold demonstrator chip, incorporating innovative features for energy harvesting and power conversion, has been designed and taped-out by ARM R&D engineers and ECS researchers.

This demonstrator, code-name “Cricket-1”, was designed as a collaboration with ARM Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Cricket-1 was taped out in September 2013, arriving back from fab in January 2014.

This advanced state-retention power-gating demonstrator, code-name “Tokachi-4A”, contains a Cortex-M0 system control processor and a dual-core Cortex-A5 application processor subsystem, again designed as a collaboration with ARM Ltd on TSMC 65nm Low-Power process technology available.

This low-power technology demonstrator, code-name “Tokachi-4M”, contains 16x Cortex-M0 CPU cores and was designed as a collaboration with ARM Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc.

This demonstrator, code-name “Tokachi-3A”, was designed as a collaboration with ARM Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3A was taped out in March 2012, packaged and delivered in July 2012 and has supported evaluation of place-and-route strategies for IP watermarking.

This demonstrator, code-name “Tokachi-3M”, was designed as a collaboration with ARM Ltd with the Physical IP designed for the 65nm Low-Power process technology available from TSMC Inc. Tokachi-3M was taped out in March 2012.

Tokachi-1 and -2 technology demonstrators were taped out and manufactured in 2011 to showcase research into register state integrity and advanced power gating and state retention techniques that build on the capabilities that are now well supported by current EDA tools and implementation flows.

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